The basic properties of a typical JFET are illustrated by the characteristic curves shown in figure 7.2. The curves shown are typical for transistors designed to work with small signals (a few tens of volts & millimamps). Note, however, that it's possible to buy a wide variety of devices which give similar shapes, but with current levels up to many amps and voltages up to hundreds of volts.
The left-hand family of curves show how the drain-source current, Ids , varies with the applied drain-source voltage, Vds , for four choices of gate-source voltage, Vgs. Broadly speaking, we can divide use these curves to divide the transistor's behaviour into two regions. Provided Vds is above some minimum value (about 2 Volts) we find that the current doesn't depend very much on the actual drain-source voltage. When it is less than this ‘turn on’ value the current does vary with the drain-source voltage. This isn't very surprising since we obviously have to apply a voltage between drain & source if we want a current to flow between them! However, once this voltage is big enough the current is almost entirely controlled by the gate-source voltage.
The reason for this can be understood by looking at the following diagrams. These show the same FET when we apply different source-drain voltages while keeping the gate-source voltage constant.
With a steady gate-source voltage of 1 V there is always 1 volt across the wall of the channel at the source end. A drain-source voltage of 1V means that there will be 2 volts across the wall at the drain end. (The drain is ‘up’ 1V from the source potential and the gate is 1V ‘down’, hence the total difference is 2V.) The higher voltage difference at the drain end means that the electron channel is squeezed down a bit more at this end.
When the drain-source voltage is increased to 10V the voltage across the channel walls at the drain end increases to 11V, but remains just 1V at the source end. The field across the walls near the drain end is now a lot larger than at the source end. As a result the channel near the drain is squeezed down quite a lot.
Increasing the source-drain voltage to 20V squeezes down this end of the channel still more. As we increase the drain-source voltage we increase the electric field which drives electrons along the open part of the channel. However, we can now see that increasing the drain-source voltage also squeezes down the channel near the drain end. This reduction in the open channel width makes it harder for electrons to pass. The two effects of greater push along the channel and a tighter squeeze tend to cancel out. As a result the drain-source current tends to remain constant when we increase the drain-source voltage.
This effect dominates the FET's behaviour when the drain-source voltage is noticeably larger than the gate-source voltage. Hence, when Vds is bigger than a few volts we get a drain-source current which doesn't depend very much on its exact value.
As we'd expect from our model of the FET, the more negative the gate, the lower the current. This is because the gate-source voltage always controls the width of the most open part of the channel at the source end. The right hand curve indicates how the Ids varies with Vgs when Vds is much bigger than 2 Volts. This curve is essentially correct for almost any drain-source voltage above a few volts. (Note of warning! There will also be a maximum voltage above which this curve won't apply. There are various reasons for this which we'll ignore in this course. Too large a voltage or current will, however, blow up the transistor. This tends to upset its behaviour!)
Before leaving our explanation of how a FET works, notice that the picture we've drawn is symmetric. i.e. in principle it doesn't matter if we swap over the drain & source connections. Some FETs can be used either way around without any noticeable change in behaviour. However, most real FETs are built with a channel wider at one end that the other. This (for reasons we won't go into) makes them work better the ‘right way around’. So, although you can use a FET with the drain and source leads swapped around, most of them don't work very well if you try it.
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University of St. Andrews, St Andrews, Fife KY16 9SS, Scotland.